This invention relates to the field of gallium nitride semiconductor devices used for high power or high temperature applications, and more specifically to a method for fabricating an n-p diode structure useful in the manufacture of a gallium nitride bipolar junction transistor.
Gallium nitride (GaN) and related binary and ternary nitride semiconductors exhibit unique properties which can be expected to provide new high power electronic devices which can operate effectively in high temperature environments. The III-V nitride semiconductors offer an attractive alternative to traditional silicon and gallium arsenide (GaAs) based electronic devices, because they exhibit significantly improved materials properties based on stronger electronic bonding and wider band gaps. Materials growth technology for GaN has advanced in recent years to produce excellent quality material for device fabrication. A particular parameter of interest for electronic applications is the large band gap of GaN (3.4 eV), which makes it an excellent candidate as an amplifier or switch which can continue to operate at temperatures approaching 600xc2x0 C. Field-effect transistor (FET) devices based on GaN have been successfully tested up to 500xc2x0 C. (S.C. Binari et al, Solid-State Electronics, vol. 41, p. 177, February 1997)
Bipolar junction transistors (BJT) are well known to have advantages over field-effect transistors for certain applications. When dealing with high power applications, the large current must pass through a commensurately large cross-sectional area. For an FET, the channel is always thin ( less than 1 micron), so the width of the device must then be very large in order to carry the current. With a BJT, the current flows in a vertical direction, and therefore the cross sectional area can be a square, and this requires less surface area on the wafer, yielding more devices per wafer. BJTs are much more linear in operation, and therefore they are well suited to analog applications. Finally, the switching speed of a BJT is determined by the thickness of the buried base, and thus photolithography precision is not an issue. However, for an FET the speed is determined by the length of the gate, and this dimension depends on the resolution of the photolithography. Because GaN can withstand high operating temperatures, these BJT transistors can be used in environments where it is difficult to provide cooling, such as on board spacecraft, in jet engines, in nuclear power plants, and at the bottom of oil wells.
Although many reports of nitride based FETs have been made, it has proven to be very challenging to make a GaN BJT. This is the result of the difficulty in preparing conducting p-type GaN. The most useful p-type dopant for GaN is magnesium (Mg). However, when GaN is grown by metal-organic chemical vapor deposition (MOCVD), there is always hydrogen present in the growth environment, and hydrogen atoms become incorporated in the crystal lattice along with each Mg atom. The hydrogen then passivates each Mg atom, and magnesium plus hydrogen fails to impart p-type conductivity to GaN. To overcome this problem, it has been necessary to anneal the sample at an elevated temperature after growth to remove the hydrogen. This has become standard practice. (S. Nakamura et al, Jpn. J. Appl. Phys., vol. 31, p. 1252, May, 1992)
However, to form a bipolar junction transistor using only MOCVD growth techniques, a layer of n-type GaN must be grown on top of the Mg-doped base to form the emitter, which becomes the third layer of the transistor. N-type GaN is impervious to the diffusion of hydrogen. Thus once the emitter layer is deposited, the base is enclosed, hydrogen is not removable, and the magnesium cannot be activated. Only if almost all of the emitter layer is removed, leaving only a tiny mesa, can the hydrogen escape from the base (See for example Lee S. McCarthy, P. Kozodoy, M. Rodwell, S. DenBaars, U. K. Mishra, WGIC Conf., Nara, Japan, Oct. 12, 1998). The drawbacks of this method are twofold. The removal of the bulk of the emitter layer is accomplished using reactive ion etching. This procedure leaves only a very small cross sectional area emitter and hence low power handling ability. This is contrary to the requirements of a BJT, which must deal with high power. In addition, the etching turns the exposed surface of the base from p-type to n-type, requiring further wet chemical etching and subsequent regrowth of new p-type material.
The present invention comprises methods for producing semiconductor devices useful in high temperature applications. The invention is based on using silicon ion implantation to convert a portion of the p-type base layer of magnesium-doped GaN into n-type GaN. The boundary of the n-type GaN within the p-type layer then becomes an np diode junction which can function as the emitter-base junction. The present methods utilize ion implantation to convert a portion of the p-type layer to n-type thereby forming an n-p junction having desirable diode characteristics.
The present method for forming an n-p diode junction comprises the following general steps:
a. providing a single crystal substrate capable of permitting growth thereon of GaN;
b. disposing a layer of p-type GaN upon the substrate;
c. annealing the p-type layer formed in (b) to remove hydrogen;
d. defining island regions in the p-type material;
e. ion implanting silicon into the island regions of the p-type material;
f. depositing an AIN capping layer onto the ion-implanted regions;
g. annealing and electrically activating the ion implanted regions thereby converting these regions to n-type; and
h. depositing metal contacts onto the n-type and p-type regions.
The present method can be applied for fabricating bipolar junction transistors utilizing the present n-p diode junctions. BJT""s typically are multilayer devices. For power applications it is important to have large areas for the junctions and a very thin middle layer for the base. Silicon ion implantation into the base (p-type material) is compatible with the need for large area. The thin base layer is controlled by simply adjusting the energy of the ions, and thus their penetration distance, such that the resulting junction depth is slightly less than the thickness of the p-type layer. Ion implantation therefore allows the fabrication of a BJT with significantly fewer process steps compared to using MOCVD growth, mesa etching, and subsequent regrowth to form the device.
A BJT according to the present invention may be fabricated according to the following general procedure:
a. providing a substrate of single crystal material capable of permitting growth thereon of gallium nitride;
b. disposing at least two layers of n-type gallium nitride upon said substrate thereby forming an n-type doped subcollector layer and an n-type doped collector layer;
c. disposing a layer of p-type gallium nitride upon said layers of n-type gallium nitride;
a. annealing said p-type layer under conditions sufficient to remove hydrogen and to form a conducting base layer;
e. defining an isolated p-type mesa thereby exposing a surface of the collector layer;
f. defining a region of said p-type mesa and said exposed n-type collector layer of gallium nitride;
g. ion implanting silicon into said region of p-type mesa thereby forming an emitter, and into exposed surface of said n-type collector layer of gallium nitride thereby providing contact with the subcollector;
h. depositing an AlN capping layer onto said silicon ion implanted regions;
i. annealing and electrically activating said silicon ion implanted regions thereby providing n-type conductivity; and
j. depositing metal contacts on the said p-type base and the said n-type emitter and collector.
In another aspect, the present invention comprises fabricating a heterojunction bipolar transistor (HBT) utilizing an n-p junction ion-implanted with silicon, aluminum and nitrogen. A process for fabricating an HBT according to the present invention comprises the following general steps:
a. providing a substrate of electrically conducting single crystal material capable of permitting growth thereon of gallium nitride;
b. disposing at least two layers of n-type gallium nitride upon said substrate thereby forming a doped subcollector layer and a doped collector layer;
c. disposing a layer of p-type gallium nitride upon said layers of n-type gallium nitride;
d. annealing said p-type layer under conditions sufficient to remove hydrogen and to form a conducting base layer;
e. defining island regions in said p-type material;
f. implanting silicon ions into said island regions of the p-type material;
g. implanting aluminum ions into said islands of the p-type material;
h. implanting nitrogen ions into said islands of the p-type material;
i. depositing an AlN capping layer onto the said silicon ion implanted surface;
j. annealing and electrically activating the silicon, aluminum, and nitrogen ion implanted regions under conditions sufficient to induce n-type conductivity and an enhanced band gap;
k. depositing metal contacts on said p-type and n-type regions; and
l. depositing metal contacts onto the underside of said conducting substrate.
The present invention includes n-p diode junctions and transistors fabricated according to the procedures defined herein.
The present methods and devices have several advantages. A first advantage is that the entire surface of the p-type layer is initially exposed and thus the hydrogen contained in the p-type layer an be readily eliminated by conventional annealing techniques, ensuring the activation of the p-type base layer. A second advantage is the simplicity of the procedure.
Ion implantation is a well-known semiconductor process technology for materials such as silicon substrates, and it has often been used to dope the material to produce a p-n junction. However, successful electrical activation of ion implanted dopants in GaN by annealing has been elusive. An essential part of the present diode-formation method is the annealing of the crystal structure damage caused by the ion implantation process. When high energy silicon ions impinge on the surface of single crystal GaN, many of the atoms of gallium or nitrogen are displaced from their natural crystal lattice locations, resulting in either an amorphous or polycrystalline layer. Thermal annealing is normally used to regrow the single crystalline film. However, until recently the annealing has not been successfull, because GaN tends to partially decompose into gallium and nitrogen at a lower temperature than would be desirable for complete annealing of the crystal. This decomposition can be reasonably controlled by adding a xe2x80x9ccappingxe2x80x9d layer of a nitride compound, for example, aluminum nitride (AlN), over the surface of the GaN prior to annealing. This cap helps to contain the nitrogen from escaping. AlN is preferred because of its inertness and compatibility with GaN. It is preferable to cap with substantially pure AlN.